1. Field of Invention
The present invention relates to a method of forming a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method of forming a hemispherical grain (HSG) polysilicon layer over the lower electrode of a DRAM capacitor so that the lower electrode has a larger surface area and hence is able to have a higher charge storage capacity.
2. Description of Related Art
A conventional DRAM cell is constructed from a MOS transistor and a capacitor. The capacitor functions as a signal storage device, and therefore plays a vital role in the operation of a DRAM cell. If the number of charges stored in a capacitor is high, noise interference when data are read from the capacitor are less and of refresh frequency is lower.
In the design of very large scale integrated (VLSI) circuits, one method of increasing a capacitor's capacitance is to increase storage node surface area. This is because capacitance value is proportional to the surface area of the storage node or electrode, which are made from a conductive material. At present, fin types or hemispherical grain structures are used to increase the surface area of storage nodes. However, manufacturing methods for fin type or hemispherical grain structures are quite complicated, and hence mass production is rather difficult. Therefore, the simpler, stacking method of increasing surface area is still employed. Nevertheless, one common method of increasing surface area and hence its charge storage capacity of a capacitor is to form a layer of hemispherical grain (HSG) polysilicon over the lower electrode.
In the conventional method of manufacturing DRAM capacitors, hemispherical grain (HSG) polysilicon is normally grown over the surface of a polysilicon lower electrode. The HSG polysilicon is a layer having a large number of hemispherical silicon grains which increases the surface area of an electrode plate.
In general, the HSG polysilicon layer is fabricated on a substrate by heating the substrate to a temperature of about 530.degree. C. so that a layer of amorphous polysilicon forms on substrate surface. This amorphous polysilicon layer is also know as .alpha.-silicon. Next, by heating to the phase transfer temperature of about 560.degree. C. to 590.degree. C., a hemispherical grain polysilicon layer is grown over the .alpha.-silicon. However, even in this temperature range, a small amount of crystalline micro-crystals will also form on the surface of the .alpha.-silicon. Hence, care must be taken to keep the phase transfer temperature below 600.degree. C., or else a large fraction of the polysilicon material will be converted to crystalline polysilicon, which has a much lower electrical conductivity.
FIGS. 1A through 1E are cross-sectional views showing the progression of manufacturing steps in fabricating the lower electrode of a capacitor using hemispherical grain polysilicon, according to a conventional method.
First, as shown in FIG. 1A, a DRAM field effect transistor 102 is formed in a substrate 100. The field effect transistor 102 includes a gate structure 104 and source/drain regions 105 and 106. The gate 104 and the source/drain regions 105, 106 are formed in the active region of the substrate 100, and are separated from neighboring devices by insulating material such as field oxide region 101. Next, an insulating layer 108 is formed over the substrate 100. The insulating layer 108 can be a silicon dioxide layer formed by chemical vapor deposition, for example. Alternatively, the insulating layer 108 can be a borophosphosilicate glass (BPSG) layer.
Thereafter, as shown in FIG. 1 B. conventional photolithographic and etching method can be used to pattern the insulating layer 108, forming an insulating layer 108a having a contact opening 109 that exposes one of the source/drain regions 106.
Next, as shown in FIG. 1C, a polysilicon layer 110 is formed over the insulating layer 108a and completely filling the contact opening 109. The polysilicon layer 110 (or .alpha.-silicon) can be formed by a chemical vapor deposition (CVD) using silane SiH.sub.4 and phosphine PH.sub.3 as the main reactive gases, for example. In order to prevent the formation of crystalline polysilicon, reaction temperature is set to a level below 530.degree. C. This reduces the possibility of forming crystalline polysilicon is to a minimum. Since the conventional temperature for depositing polysilicon must be below 530.degree. C., polysilicon deposition takes longer.
In general, impurities can be implanted into the polysilicon layer 110 to increase its electrical conductivity. Next, a patterned photoresist layer 114 is formed over the polysilicon layer 110. The patterned photoresist layer 114 acts as a mask for patterning the polysilicon layer 110 in the subsequent step.
Next, as shown in FIG. 1D, conventional photolithographic and etching methods, for example, a dry etching method (that is, a plasma etching method), are used to pattern the polysilicon layer 110 into a portion of the lower electrode. The polysilicon layer 110 is etched to form a polysilicon layer 110a; etching continues until the insulating layer 108a is exposed. When the polysilicon layer 110 is plasma-etched, the sidewall surfaces 116a of the polysilicon layer 110a are also bombarded. Hence, the sidewall surfaces 116a become more amorphous.
Next, as shown in FIG. 1E, the photoresist 114 is removed. Because the top surface of the polysilicon layer 110a is covered by the photoresist layer 114 in the previous plasma-etching operation, a fraction of the micro-crystals still exists on the surface of the hemispherical grain polysilicon. Therefore, distribution of hemispherical grain polysilicon on the polysilicon layer 110a cannot be uniform. Even though the temperature is now raised to about 560-590.degree. C. to create more hemispherical grain polysilicon, top surface 116b of the polysilicon layer 110a already contains previously formed micro-crystals. In the presence of previously formed micro-crystals, it is difficult to increase effective surface area on the top surface 116b of the polysilicon layer 110a.
Although the aforementioned method of forming a stacked type of capacitor is simple, the resulting surfaces of the conductor layer that functions as the lower electrode have a non-uniform distribution of hemispherical grain polysilicon due to the presence of micro-crystals. Therefore, the effective surface of the stacked DRAM capacitor fabricated with a layer of hemispherical grain polysilicon on its electrode is lower than expected, and hence capacity to store charges in the capacitor is reduced. Moreover, the deposition temperature for depositing polysilicon must be below 530.degree. C., which lengthens deposition time.
In light of the foregoing, there is a need to improve the fabrication method for the lower electrode of a DRAM capacitor.